This invention addresses two separate physical leakage pathways in CMOS circuits: mid-infrared thermal emission and near-infrared photon emission. The invention integrates two mechanisms into standard back-end-of-line fabrication processes to provide a unified method for reducing optical side-channel vulnerability without altering the performance of the CMOS logic or requiring changes to front-end device structures. Background: Optical side channel attacks exploit unintentionally emitted radiation from integrated circuits to infer internal computational activity. One instance of these attacks occurs when thermal infrared imaging detects minute temperature variations on the chip surface, which reveal patterns that correlate with switching activity. Another instance of these attacks uses near-infrared photon emission produced by hot-carrier recombination during transistor switching. Weak emissions can escape through the backside of a thinned die and be recorded using NIR detectors, enabling spatially resolved observation of logic activity. Existing mitigation techniques focus on packaging-based shielding, chip-level opaque coatings, or algorithmic countermeasures such as randomization and noise injection. These approaches are often costly, limited ineffectiveness, or incompatible with high-performance system requirements. Applications:
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