PRISM: Priority-first Repair with Intelligent Spare Mapping

As the semiconductor industry transitions from monolithic dies to chiplet-based architectures, interconnect density has increased dramatically, making copper pillars and redistribution layers more susceptible to defects such as voids, delamination, and bridging shorts. Conventional repair approaches, including those defined by the Universal Chiplet Interconnect Express (UCIe) standard, rely on static redundancy with only a limited number of dedicated spare links. While effective for isolated failures, these methods struggle to accommodate multiple faults that arise under manufacturing variations or operational stress. As a result, even a small number of interconnect failures can render an entire multi-chiplet package unusable, leading to significant yield loss and increased manufacturing costs. Recent advances in finite-element defect modeling and built-in self-test (BIST) architectures have not only improved the understanding of interconnect failure mechanisms but have also demonstrated the potential for more adaptive and intelligent repair strategies that can better preserve system functionality.

 

Researchers at Arizona State University have developed PRISM (Priority-first Repair with Intelligent Spare Mapping), an innovative dynamic repair framework designed for chiplet-to-chiplet interconnects within fan-out wafer-level packaging (FOWLP). PRISM employs real-time rerouting of faulty signals, prioritizing critical signals through a built-in self-test (BIST) and a priority-based repair algorithm. This enables flexible spare reuse and strategic spare allocation without modifying the physical I/O layer, significantly improving repair coverage and package functionality in high-density semiconductor systems. This framework implements demonstrates scalability with low area and power overhead, making it suitable for advanced multi-chiplet systems.

 

PRISM represents a dynamic repair framework that enhances the reliability and yield of fan-out wafer-level packaging in multi-chiplet systems.

 

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